1. Field of the Invention
This invention relates to a system and method for mapping a selected subset of elements of a first set of elements into a second set of elements and more particularly to an address translator for a large core memory wherein each memory address corresponds to a different element and defective address locations form the subset.
2. Discussion of the Prior Art
Previously known mapping systems divide an input set of states which represent a set of elements into small groups and selectively provide a mapping for each group. This is relatively wasteful of capacity in that a maximum possible mapping capability must be provided for each group even though most of the capability will not be used. For example, 512K input states might be divided into 512 groups of 1K states each. If the average number of mappings is 4 per group, a mapping capacity on the order of 40 or more would be rquired for each group to accommodate worst case conditions. This results in a total mapping capacity of 20,000 although only 2000 states may actually be mapped. Furthermore, the larger the input set the greater the probability that the maximum capacity will be exceeded at one of the groups.
The present invention economically permits the mapping of the entire input set as a whole. The bigger the input set, the more efficient the hardware is and the less likely that the number of states to be mapped will exceed the anticipated maximum number of states.
The present system has particular advantage as an address translator for input addresses for a large memory wherein each address represents an input state or element. Up to now it has been necessary, whenever a memory defect occurs, to repair or replace the section of memory containing the defect. In the case of a semiconductor memory, this may result in the loss of many thousands of bits of memory capacity on a memory "chip" because of a single defect. In the case of a core memory tiny wires passing through hundreds of cores must be withdrawn, a defective core replaced and the wires rethreaded. Not only is this rework very expensive, but the process of withdrawing and rethreading the cores may inflict additional damage on the memory. To minimize rework, each core is pre-inspected or graded. This inspection is expensive and the extra handling required thereby inflicts extra damage on some of the cores.
The present invention has resulted in the building of a large 512K word by 18 bit core memory without grading the cores prior to stack assembly and without any rework after stack assembly. The elimination of stack rework has further facilitated an advantageous high density stack arrangement that would not be suitable if rework were required.